1. Field of the Invention
The present invention relates to the arrangement of a semiconductor memory device, a more specifically, to the arrangement of a redundancy determination circuit in a semiconductor memory device.
2. Description of the Background Art
In general, in a semiconductor memory device, a redundant memory cell array is provided in order to repair a defective memory cell within a memory cell array that is produced during the manufacturing process, and the so-called redundancy repair is performed in which the defective memory cell is replaced by a memory cell within the redundant memory cell array.
In this case, a redundancy determination circuit is provided for storing the address information of the memory cell column or the memory cell row in which the defective memory cell resides in advance within the semiconductor memory device by using an element, such as a fuse element, capable storing the information in a non-volatile manner, and for determining whether an address signal provided from the outside matches the defective row address or the defective column address, and when a match occurs, for stopping the selecting operation for a normal memory cell array and instead activating the selecting operation for the redundant memory cell array.
While the demand for a higher operation speed of the semiconductor memory device intensifies, due to such redundancy determination, the access time for the address to which redundancy replacement is performed tends to degrade in general in comparison with the case in which a normal memory cell is selected.
As it is, although the defective memory cell can be repaired by the redundant memory cell array, the requirement specification of a product cannot be satisfied with regard to the operation speed.
A conventional semiconductor memory device and its problems will be described in further detail below.
FIG. 14 is a schematic block diagram related to the description of the circuit arrangement for selecting a memory cell row within a memory cell array in a conventional semiconductor memory device. For simplicity of description, a row address signal provided to row and column address buffer 224 consists of 8 bits of address signals A&lt;0&gt; to A&lt;7&gt;.
For simplicity, a normal memory cell array is provided with 256 word lines WL, and a redundant memory cell array provided corresponding to the normal memory cell array is provided with four redundant memory cell rows to which four redundant word lines SWL are correspondingly arranged.
As shown in FIG. 14, the respective address latch circuits 210.0 to 210.7 correspondingly provided for address signals A&lt;0&gt; to A&lt;7&gt; latch the corresponding address signals when a signal ZRAL is in the active state, and output internal address signals RA&lt;0&gt;, ZRA&lt;0&gt;, RA&lt;1&gt;, ZRA&lt;1&gt;, . . . RA&lt;7&gt;, ZRA&lt;7&gt; according to a signal RADE.
For instance, address latch 210.0 receives an address signal A&lt;0&gt; and outputs internal address signals RA&lt;0&gt; and ZRA&lt;0&gt;.
A row predecoder 226 receives internal address signals RA&lt;0&gt;, ZRA&lt;0&gt; to RA&lt;7&gt;, ZRA&lt;7&gt; output from address latch circuits 210.0 to 210.7, and outputs predecode signals XA&lt;0:3&gt;, XB&lt;0:3&gt;, XC&lt;0:3&gt;, and XD&lt;0:3&gt;.
On the other hand, a spare determination circuit 240 receives address signals A&lt;2:7&gt; (=A&lt;2&gt; to A&lt;7&gt;) upon activation of signal ZRAL, and according to signal RADE, outputs a comparison result with a defective row address stored in advance. A logic gate 232 receives a signal RXT and a determination signal output from spare determination circuit 240, and outputs a signal NRE which attains the active state (the logic high or "H" level) when no match is detected between address signals A&lt;0&gt; to A&lt;7&gt; and a redundant memory cell row address as a result of spare determination and which attains the inactive state (the logic low or "L" level) when the match with the redundant memory cell row address is detected.
On the other hand, a logic gate 234 receives signal RXT and an output from spare determination circuit 240, and outputs a signal SRE which attains the active state ("H" level) when a match occurs between a redundant memory cell row and address signals A&lt;0&gt; to A&lt;7&gt; provided from the outside and which attains the inactive state ("L" level) when no match occurs.
A normal row decoder 241 receives predecode address signals XA&lt;0:3&gt; to XD&lt;0:3&gt;, and activates one of word lines WL&lt;0:255&gt; (WL&lt;0&gt; to WL&lt;255&gt;) within a corresponding normal memory cell array when signal NRE is in the active state.
A redundant row decoder 242, on the other hand, receives a predecode signal XA&lt;0:3&gt; and signal SRE, and activates one of redundant word lines SWL&lt;0:3&gt; (SWL&lt;0&gt; to SWL&lt;3&gt;) within a redundant memory cell block RCBi according to the activation of signal SRE when the redundant memory cell row and the address signal provided match in spare determination circuit 240.
FIG. 15 is a schematic block diagram related to the description of the arrangement of spare determination circuit 240 shown in FIG. 14.
Spare determination circuit 240 is provided with a delay circuit 3002 for receiving signal RADE and outputting signal RADE as a signal RADED after the delay of a prescribed period of time, a defective address comparing portion 3010 for storing a defective address row in advance and receiving input predecode signals XB&lt;0&gt;, XB&lt;1&gt;, XC&lt;0&gt; to XC&lt;3&gt;, and XD&lt;0&gt; to XD&lt;3&gt; to output a comparison result, a P-channel MOS transistor TP110 for selectively supplying a power-supply potential Vcc to defective address comparing portion 3010 according to signal RADED, an inverter INV110 for receiving an output from an output node n101 of defective address comparing portion 3010, a P-channel MOS transistor TP111 connected between power-supply potential Vcc and node n101 for receiving an output from inverter INV110 at a gate, and an inverter INV111 for receiving an output from inverter INV110 to output a signal SREF.
Defective address comparing portion 3010 includes a fuse element F3100.0 and an N-channel MOS transistor TN3100.0, a fuse element F3100.1 and an N-channel MOS transistor TN3100.1 to a fuse element F3100.15 and an N-channel MOS transistor TN3100.15, respectively connected in series between node n101 and a ground potential GND.
Gates of transistors TN3100.0 to TN3100.15 respectively receive predecode signals XB&lt;0&gt;, XB&lt;1&gt;, XC&lt;0&gt; to XC&lt;3&gt;, and XD&lt;0&gt; to XD&lt;3&gt;.
FIG. 16 is a timing chart related to the description of an operation of a circuit for selecting a cell row shown in FIG. 14.
When an address signal is provided from the outside, according to the activate state of signal ZRAL at time t0, address latches 210.0 to 210.7 latch in address signals A&lt;0&gt; to A&lt;7&gt;.
Thereafter, according to the activation of signal RADE at time t1, signal ZRAL enters the inactive state at time t2. At time t3 when the time margin including the waiting time for a result of the determination of the redundant row and the delay time required for a predecode operation and the like has elapsed since signal ZRAL entered the inactive state, signal RXT for instructing the start of a selecting operation of a word line is activated.
In other words, such time margin must be allowed from the inactivation of signal ZRAL to the activation of signal RXT so that a row select operation would be delayed for the time required for a redundant row replacement.